1. Field of the Invention
The invention generally relates to electronics, and in particular, to interfacing between circuits of disparate logic families.
2. Description of the Related Art
Various logic families and signaling technologies exist. To allow for backwards compatibility with older equipment or with requirements specifying these older standards, it can be necessary for a device fabricated with a modern CMOS process to provide and/or receive signaling that is compatible with older signaling technology.
FIG. 1 illustrates voltage levels for a variety of signaling technologies. Voltage is expressed along a vertical axis. Time and a variety of signaling technologies are expressed along a horizontal axis. As illustrated in FIG. 1, emitter coupled logic (ECL), positive ECL (PECL), low-voltage positive ECL (LVPECL), and current mode logic (CML) are examples of these older signaling technologies. The signaling technologies described herein can be single-ended or can be differential, that is, have both a true and a false version of the signal. In addition, some of these signaling technologies are not standardized, which can make backwards compatibility even more challenging.
Depending on the application, the signaling signals can be capacitively (AC) coupled or can be direct current (DC) coupled. An example of AC coupling is shown in FIG. 5. It is typically straightforward to interconnect disparate signaling technologies using AC coupling.
However, DC coupling from a modern CMOS integrated circuit (CMOS IC) to an older signaling technology can be difficult. As illustrated in FIG. 1, these older signaling technologies can use different voltage levels than is typically used in a modern CMOS IC. In addition, as illustrated in FIG. 2, there is a limit on maximum working voltage for modern small-geometry devices. In addition, the power consumption associated with the relatively high DC voltage levels of older signaling technologies can be prohibitively high compared with the relatively low power consumption that can be attained by AC-coupled low voltage CMOS drivers and receivers.
Emitter Coupled Logic (ECL)
ECL is a relatively old logic family that has evolved into many families, including 10k, 100k, ECLinPS and RSECL. ECL can be considered to be a de facto standard, but is also specified by ANSI/TIA/EIA-612 “Electrical Characteristics for an Interface at Data Signaling Rates to 52 Mbit/s” as well as a sub-clause within the HIPPI (High-Performance Parallel Interface) ANSI standard.
ECL signals can be used either single-ended or differentially and typically generate between 700 millivolt (mV) to 800 mV peak-differential at the transmitter output. ECL transmitters have low output impedance due to open emitter driver circuits that are operated in the active region, thus providing very fast edge rates. The output is typically terminated into 50Ω to a voltage that is 2 volts below ground (or the positive rail). ECL components are usually powered between ground (positive rail) and −5.2 V (negative rail). Other ECL configurations can be single or double terminated, but are typically terminated only at the receiver end with external resistors.
FIG. 3 illustrates a typical bipolar implementation of an ECL input/output circuit, and FIG. 4 illustrates corresponding input/output levels. Because of voltage level incompatibilities between CMOS and ECL, for example, CMOS uses positive voltages whereas ECL uses negative voltages, CMOS and ECL are typically interconnected using AC coupling with coupling capacitors as illustrated in FIG. 5.
However, with a CMOS process that supports Deep N-well and retrograde P-wells (assuming a P-substrate), it is possible to have a DC coupled connection as illustrated in FIG. 6, assuming that the MOS devices can withstand the DC voltages as described earlier in connection with FIG. 2.
The primary areas of high power consumption are: 1) termination; and 2) output drive and pre-drive stages. The termination power consumption corresponds to the power in the input termination resistors. FIGS. 7A-7C illustrate various examples of termination. Table 1 summarizes applicable resistor values for various voltage levels.
TABLE 1Termination Resistor Values|VCC − VEE| =|VCC − VEE| =|VCC − VEE|=2.5 V3.3 V5 VR124912782.5R261.982.5124RT49.949.949.9RT12146.4113
VCC and VEE can be analogous to VDD and VSS. The VTT supply termination illustrated in FIG. 7B will have slightly more power than the Y connection illustrated in FIG. 7C unless a switching regulator is used (due to regulator overhead). The termination power consumption can be calculated as shown in Equations 1A-1E.
                              Power                                    R              ⁢                                                          ⁢              1                        ,                          R              ⁢                                                          ⁢              2                                      ≈                  2          *                                                                                      VCC                  -                  VEE                                                            2                                                      R                ⁢                                                                  ⁢                1                            +                              R                ⁢                                                                  ⁢                2                                                                        (                              Eq            .                                                  ⁢            1                    ⁢          A                )                                          Power                      RT            ,                          RT              ⁢                                                          ⁢              1                                      ≈                                                                                              VIL                  -                  VTT                                                            2                        RT                    +                                                                                      VIH                  -                  VTT                                                            2                        RT                    +                                                                                      VTT                  -                  VEE                                                            2                                      RT              ⁢                                                          ⁢              1                                                          (                              Eq            .                                                  ⁢            1                    ⁢                                          ⁢          B                )            VTT=VCC−2  (Eq. 1C)VIL=VCC−1.6425  (Eq. 1D)VIH=VCC−1.0225  (Eq. 1E)
The output stage power consumption is 15.4 mA*|VCC−VEE|. Hence, the sum of the termination power consumption and the output stage power consumption (termination power consumption figures include a standard linear regulator power if applicable and output stage power) is as shown in Table 2.
TABLE 2Termination Power|VCC − VEE|Typical Power (mW)VoltageR1, R2RT, RT1RT, VTT2.57972 72+3.3155109109+5319178178+Positive Emitter Coupled Logic (PECL)
The PECL family uses a positive 5 V rail to ground for the voltage bias supplies rather than the ground to −5.2 V voltage bias that is used by some other families of ECL, such as the 10 KH family. A conventional technique to interconnect a CMOS interface to a PECL circuit is shown in FIGS. 8A and 8B, and assumes that the MOS devices are able to withstand the DC voltages present. The primary areas of high power consumption are again: 1) termination; and 2) output drive and pre-drive stages. The power consumption of the CMOS to PECL interconnection is about the same as for the 5V ECL case described earlier in connection with Table 2.
Low Voltage Positive Emitter Coupled Logic (LVPECL)
The LVPECL family is PECL with a positive 3.3 V rail to ground for the voltage biases instead of the positive 5 V rail to ground that used by PECL. A conventional technique to interconnect a CMOS interface to a PECL interface described earlier in connection with FIGS. 8A and 8B is also applicable to LVPECL, and assumes that the MOS devices are able to withstand the DC voltage levels present. The primary areas of high power consumption are: 1) termination; and 2) output drive and pre-drive stages. The power consumption of the CMOS to LVPECL interconnection is about the same as for the 3.3V ECL case described earlier in connection with Table 2.
Current Mode Logic (CML)
CML signaling technology is not standardized. However, there are two common-used CML configurations referred to as: 1) 3.3 V CML and 2) 1.2 V CML. These two common types are the similar except for the positive voltage used. CML is similar to PECL, but without the open emitter device. A conventional example of CML signaling implemented with bipolar transistors is illustrated in FIG. 9. CML uses resistors for pull ups and switches current for pull down. As such, it is simpler than ECL/PECL and as it has both Tx and Rx termination as part of the driver/receiver, it typically has better signal integrity (SI) than ECL/PECL and can typically operate at higher speeds than ECL/PECL. The signal swing can vary in a relatively wide range, but most configurations use a 400 mV peak differential swing. FIGS. 10A and 10B illustrate a conventional CMOS implementation of CML assuming that the MOS devices can withstand the DC voltages present.
The primary areas of high power consumption are: 1) termination and output drive; and 2) pre-drive and level shifter stages. However, the power consumption of the pre-driver and level shifter is relatively small compared to the termination and output drive, and can thus be ignored for analysis. FIG. 11 illustrates a typical termination power for both the 1.2 V and the 3.3 V CML interface cases.
CMOS Voltage Mode Driver
A CMOS Voltage Mode Driver is described in commonly-owned U.S. Pat. No. 7,501,851. FIG. 12 herein illustrates a relatively large CMOS inverter with series resistors RT used to partially set the output impedance of the driver. The driver is not the signaling interface itself, but rather a technique to drive a signaling interface. Control of the Tgates permits the output impedance to be corrected and the output swing to be varied.
The CMOS Voltage Mode Driver can be used within CMOS devices, along with external AC coupling, to separate the driver common mode (VDD_driver/2) level from the receiver common mode level. The power consumption is relatively low as illustrated in FIG. 13 and in Table 3.
TABLE 3AC Coupled Voltage Mode Termination Power (mW)VDD Voltage of Modern CMOSProcesses0.8 V0.9 V1 V1.2 VOutput Voltage swing (Vppd)0.80.91.01.2Driver Termination Power1.62.02.53.6Receiver Termination Power1.62.02.53.6Total Termination Power3.24.15.07.2